KUALA LUMPUR, Dec 5 (Bernama) -- Bursa Malaysia closed lower on Friday amid mixed regional market performance as investors turned cautious over a possible rate hike by the Bank of Japan (BOJ) and upcoming US economic data that may influence the Federal Reserve’s (Fed) interest rate decision next week. At 5 pm, the FTSE Bursa Malaysia KLCI (FBM KLCI) pared most earlier losses to settle 4.55 points easier, or 0.28 per cent, to 1,616.52 from Thursday’s close of 1,621.07. The benchmark index, which opened 0.37 of-a-point lower at 1,620.70, moved between 1,609.67 and 1,621.25 throughout the day. The broader market was negative, with decliners outpacing advancers 604 to 439. A total of 550 counters were unchanged, 1,151 untraded, and 18 suspended. Turnover declined to 3.17 billion units worth RM2.24 billion from 4.48 billion units worth RM2.75 billion yesterday. Rakuten Trade Sdn Bhd vice-presiden...
Tackling High Power Demand
The computing chips that power artificial intelligence are among the most energy-hungry technologies today. Taiwan Semiconductor Manufacturing Co (TSMC), the world’s largest contract chipmaker and key supplier to Nvidia, is spearheading efforts to make AI chips as much as 10 times more energy efficient.
At a Silicon Valley conference on Wednesday, TSMC showcased its strategy to redesign chips using AI-driven software tools that can deliver significant efficiency gains. For context, Nvidia’s flagship AI servers consume up to 1,200 wattsunder heavy workloads — equivalent to the continuous power needs of about 1,000 US homes.
Chiplet Designs and AI Tools
The push centers on a new generation of designs where multiple “chiplets” — smaller specialized components — are combined into a single advanced package. To optimize these complex designs, TSMC is working closely with electronic design automation (EDA) leaders Cadence Design Systems and Synopsys.
Both firms unveiled new AI-powered chip design products developed in partnership with TSMC. In testing, these tools outperformed human engineers on certain design tasks, finding better solutions in minutes instead of days.
“That helps to max out TSMC technology’s capability, and we find this very useful,” said Jim Chang, deputy director of TSMC’s 3DIC Methodology Group.
Overcoming Physical Limits
As chip performance scales, traditional manufacturing approaches are facing bottlenecks, especially in moving data on and off chips through electrical connections. Optical interconnects — using light instead of electricity — are seen as a potential breakthrough but still require reliability improvements for use in massive data centers.
“Really, this is not an engineering problem. It’s a fundamental physical problem,” said Kaushik Veeraraghavan, an engineer at Meta Platforms’ infrastructure group, during his keynote.
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